TC518512PL-10LV中文資料東芝數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The TC518512PL is a 4M bit high speed CMOS pseudo static RAM organized as 524,288 words by 8 bits. The TC518512PL

utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power

storage. The TC518512PL-LV operates from a single 3.0V-5.5V power supply. Refreshing is supported by a refresh (OE/RFSH)

input which enables two types of refreshing - auto refresh and self refresh. The TC518512PL features a static RAM-like interface

with a write cycle in which the input data is written into the memory cell at the rising edge of R/W thus simplifying the microproces-

sor interface.

The TC518512PL is available in a 32-pin, 0.6 inch width plastic DIP, a small outline plastic flat package, and a thin small outline

package (forward type, reverse type).

Features

Organization: 524,288 words x 8 bits

Low voltage operation: 3.0V-5.5V

? Data retention supply voltage: 3.0V-5.5V

Fast access time

ICEA CE Access Time

LOEA OE Access Time

tac Cycle Time

Power Dissipation

Self Refresh Current

Self Refresh Current

5.5V

3.0V

TC518512PL-LV Family

-70

-80

70ns

80ns

30ns

30ns

115ns

130ns

385mW 330mW

200μA

100μA

Auto refresh is supported by an internal refresh address

counter

Self refresh is supported by an internal timer

Inputs and outputs TTL compatible

Refresh: 2048 refresh cycles/32ms

? Package

- TC518512PL: DIP32-P-600

- TC518512FL: SOP32-P-525

- TC518512FTL: TSOP32-P-400

- TC518512TRL: TSOP32-P-400A

-10

100ns

40ns

160ns

275mW