TC518512PL-70DR中文資料東芝數(shù)據(jù)手冊(cè)PDF規(guī)格書

Description

The TC518512PL is a 4M bit high speed CMOS pseudo static RAM organized as 524,288 words by 8 bits. The TC518512PL utilizes

a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, .!J!gh speed and low power storage. The

TC518512PL operates from a single 5V power supply. Refreshing is supported by a refresh (OEIRFSH) input which enables two

types of refreshing - auto refresh and self refresh. The TC518512PL features a static RAM-like interface with a write cycle in which

the input data is written into the memory cell at the rising edge of RNV thus simplifying the microprocessor interface.

The TC518512PL is available in a 32-pin, 0.6 inch width plastic DIP, a small outline plastic flat package, and a thin small outline

package (forward type, reverse type).

Features

? Organization: 524,288 words x 8 bits

? Single 5V power supply

? Data retention supply voltage: 3.0V - 5.5V

? Fast access time

TC518512PL-(DR) Family

-70 ·80 ·10

tCEA cr Access Time 70ns 80ns 100ns

toEA OE Access Time 30ns 30ns 40ns

tRC Cycle Time 11Sns 130ns 160ns

Power Dissipation 38SmW 330mW 27SmW

!S.SV 200!lA

Self Refresh Current !

3.0V 100!lA

? Auto refresh is supported by an internal refresh address

counter

? Self refresh is supported by an internal timer

? Inputs and outputs TIL compatible

? Refresh: 2048 refresh cycles/32ms

? Package

- TC518512PL: DIP32-P-600

- TC518512FL: SOP32-P-525

? TC518512FTL: TSOP32 -P-400

? TC518512TRL: TSOP32-P-400A