TC51V4260DFTS中文資料東芝數(shù)據(jù)手冊PDF規(guī)格書

Description

The TC51V4260DFTS is the new generation dynamic RAM organized 262,144 word by 16 bits. The TC51V4260DFTS uti-

lizes Toshiba's CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating

margins, both internally and to the system user. Multiplexed address inputs permit the TC51V4260DFTS to be packaged

in a standard 44/40 pin plastic TSOP. The package size provides high system bit densities and is compatible with widely

available automated testing and insertion equipment. System oriented features include single power supply of 3.3V+0.3V

tolerance, direct interfacing capability with high performance logic families such as Schottky TTL.

Features

? 262,144 word by 16 bit organization

? Fast access time and cycle time

? Single power supply of 3.3V+0.3V with a built-in VBB

generator

? Low Power

342mW MAX. Operating

(TC51V4260DFTS-60)

288mW MAX. Operating

(TC51V4260DFTS-70)

- 5.5mW MAX. Standby

Outputs unlatched at cycle end allows two-dimensional

chip selection

? Read-Modify-Write, CAS before RAS refresh, RAS-only

refresh, Hidden refresh, Self refresh, and Fast Page

Mode capability

All inputs and outputs TTL compatible

? 512 refresh cycles/64ms

? Package

TC51V4260DFTS: TSOP44-P-400B

Note: For packaging details see Mechanical Dimensions section.