TC551402J-25中文資料東芝數(shù)據(jù)手冊PDF規(guī)格書

Description

The TC551402J is a 4,194,304 bit high speed CMOS static random access memory that is configurable to an organization of

either 4,194,304 words by 1 bit or 1,048,576 words by 4 bits when power is initially applied to the device. The mode (x1/x4) is

selected by the input level of pin 17 (B1/B4). The TC551402J operates from a single 5V supply. Toshiba's advanced CMOS tech-

nology and circuit design enable high speed operation.

The TC551402J features low power dissipation when the SRAM is deselected using chip enable (CE), and has an output

enable input (OE) for fast memory access. It is suitable for use in high speed applications such as cache memory, high speed stor-

age, and main memory. All inputs and outputs are TTL compatible.

The TC551402J is available in a 32-pin, 400mil SOJ package suitable for high density assembly.

Features

? Fast access time

- TC551402J-20

- TC551402J-25

TC551402J-30

? Low power dissipation

Operation:

TC551402J-20

TC551402J-25

-TC551402J-30

20ns (max.)

25ns (max.)

30ns (max.)

160mA (max.)

160mA (max.)

150mA (max.)

10mA (max.)

- Standby:

Fully static operation

Single power supply: 5V±10

Output buffer control: OE

? Inputs and outputs TTL compatible

Separate data I/O (x1 mode)

Common data I/O (x4 mode)

? Package

TC551402J: SOJ32-P-400A