TC55257BPL-10LT中文資料東芝數據手冊PDF規(guī)格書

Description

The TC55257BPL is a 262,144 bit CMOS static random access memory organized as 32,768 words by 8 bits and operated from a

single 5V power supply. Advanced circuit techniques provide both high speed and low power features with an operating current of

5mNMHz (typ.) and a minimum cycle time of 85ns.

When CE is a logical high, the device is placed in a low power standby mode in which the standby current is 2~ at room temperature. The TC55257BPL has two control inputs. Chip enable (CE) allows for device selection and data retention control, while an

output enable input (OE) provides fast memory access. The TC55257BPL is suitable for use in microprocessor systems where high

speed, low power, and battery backup are required. The TC55257BPL-(LT) has an operating temperature range of -20 - 7CfC so it

is suitable for use in low temperature applications.

The TC55257BPL is offered in a standard dual-in-line 28-pin plastic package (0.6/0.3 inch width), a small outline plastic package, and a thin small outline plastic package (forward type, reverse type).

Features

? Low power dissipation:

? Standby current:

? Single 5V power supply

? Access time (max.)

27.5mW/MHz (typ.)

100~(max.)

TC55257BPL/ TC55257BPL/

B FL/BS PL/B FTL/ BFL/BSPL/BFTL/

BTRL-85(LT) BTRL-10(LT)

Access Time

Chip Enable Access Time

Output Enable Time

? Power down feature: CE

? Data retention supply voltage:

? Wide operating temperature:

? Inputs and outputs TIL compatible

85ns

85ns

45ns

2.0 - 5.5V

-20 - 70°C

100ns

100ns

50ns

? Package TC55257BPL(LT): DIP28-P-600

TC55257BFL(LT) : SOP28-P-450

TC55257BSPL(LT) : DIP28-P-300B

TC55257BFTL(LT) : TSOP28-P

TC55257BTRL(LT) : TSOP28-P-A