TC55B328P-10中文資料東芝數(shù)據(jù)手冊(cè)PDF規(guī)格書

Description

The TC55B328P/J is a 262,144 bit high speed BiCMOS static random access memory organized as 32,768 words by 8 bits and

operated from a single 5V supply. Toshiba's BICMOS technology and advanced circuit design enable high speed operation.

The TC55B328P/J features low power dissipation when the device is deselected using chip enable (CE) and has an output

enable input (OE) for fast memory access.

The TC55B328P/J is suitable for use in high speed applications such as cache memory and high speed storage. All inputs and

outputs are TTL compatible.

The TC55B328P/J is available in a 300mil width, 28-pin DIP and SOJ suitable for high density surface assembly.

Features

? Fast access time

- TC558328P/J-10

- TC558328P/J-12

10ns (max.)

12ns (max.)

? Low power dissipation

- Operation:

170mA (max.)

- TC55B328P/J-10

- TC55B328P/J-12

Standby:

170mA (max.)

15mA (max.)

Single 5V power supply: 5V±10

? Fully static operation

? Inputs and outputs TTL compatible

Output buffer control: OE

?

? Package:

- TC55B328P: DIP28-P-300B

TC55B328J: SOJ28-P-300A