TC55BS8125J中文資料東芝數(shù)據(jù)手冊PDF規(guī)格書

Description

The TC55BSB125J is a 1,048,576 bit synchronous static random access memory fabricated using BICMOS technology and

organized as 131,072 words by 8 bits. The TC55BS8125J is similar to the TC55BS8128J but has common data I/O lines and

does not have the write-cycle pass-through feature.

Designed for pipelined architectures, this device has internal input and output registers which latch on the positive edge of an

external clock (CLK). All address, data, and control signals are latched. The setup and hold times for the inputs are 2ns and 1ns

respectively. Synchronous SRAMS can lead to faster, more robust system operation by virtually eliminating the timing skew

problems associated with conventional asynchronous SRAMS. For example, write operations are internally self-timed when

initiated - eliminating the need for accurate write pulse generation and timing by the memory controller or microprocessor. For

read cycles, data is available one clock cycle after the address is latched. All inputs and outputs are TTL compatible.

The TC55BS8125J is available in a 36-pin, 400mil SOJ package suitable for high density assembly.

Features

? Fast cycle time

- TC55BS8125J-10

- TC55BS8125J-12

Fast clock access time

- TC55BS8125J-10

- TC55BS8125J-12

10ns (max.)

12ns (max.)

5ns (max.)

6ns (max.)

Input and output registers for synchronous operation

Single power supply: 5V±10

? Common data I/O

? Package: JEDEC standard pinout

36-pin, 400mil SOJ: SOJ36-P-400