TC55V1864J_V01中文資料東芝數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The TC55V1864J/FT is a 1,179,648 bit high speed CMOS static random access memory organized as 65,536 words by 18 bits

and operated from a single 3.3V supply. Toshiba's advanced CMOS technology and circuit design enable high speed operation.

The TC55V1864J/FT features low power dissipation when the device is deselected using chip enable (CE), and has an output

enable input (OE) for fast memory access. Byte access is supported by upper and lower byte controls.

The TC55V1864J/FT is suitable for use in high speed applications such as cache memory and high speed storage. All inputs and

outputs are LVTTL compatible.

The TC55V1864J/FT is available in a 400mil width, 44-pin plastic SOU and thin small outine package (forward type) suitable for

high density surface assembly.

Features

Fast access time

- TC55V1864J/FT-10

- TC55V1864J/FT-12

- TC55V1864J/FT-15

Low power dissipation

Cycle Time

10ns (max.)

12ns (max.)

15ns (max.)

10

12 15 20 30

Operation (max.) 260 220 200 180 150

- Standby:

1mA (max.)

? Single 3.3V power supply: 3.3V+0.3V

? Fully static operation

? Inputs and outputs LVTTL compatible

Output buffer control:

Data byte controls:

OE

LB, UB

? Package

- TC55V1864J: SOJ44-P-400

- TC55V1864FT: TSOP44-P-400

ns

mA