TC58NVG5D2ELA48中文資料東芝數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The TC58NVG5D2 is a single 3.3 V 32 Gbit (36,393,025,536 bits) NAND Electrically Erasable and Programmable

Read-Only Memory (NAND E2PROM) organized as (8192 + 376) bytes × 128 pages × 4148 blocks.

The device has two 8568-byte static registers which allow program and read data to be transferred between the

register and the memory cell array in 8568-byte increments. The Erase operation is implemented in a single block

unit (1 Mbytes + 47 Kbytes: 8568 bytes × 128 pages).

The TC58NVG5D2 is a serial-type memory device which utilizes the I/O pins for both address and data

input/output as well as for command inputs. The Erase and Program operations are automatically executed making

the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still

cameras and other systems which require high-density non-volatile memory data storage.

FEATURES

? Organization

TC58NVG4D2E

Memory cell array 8568 × 518.5K × 8

Register 8568 × 8

Page size 8568 bytes

Block size (1M + 47 K) bytes

? Modes

Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,

Multi Page Program, Multi Block Erase, Multi Page Copy, Mullti Page Read

? Mode control

Serial input/output

Command control

? Number of valid blocks

Min 3936 blocks

Max 4148 blocks

? Power supply

VCC = 2.7 V to 3.6 V

? Access time

Cell array to register 200 μs max

Serial Read Cycle 25 ns min

? Program/Erase time

Auto Page Program 1600 μs/page typ.

Auto Block Erase 4.5 ms/block typ.

? Operating current

Read (25 ns cycle) TBD ( 65 to 70) mA max.

Program (avg.) TBD ( 65 to 70)mA max.

Erase (avg.) TBD ( 65 to 70)mA max.

Standby 100μA max

? Package

(Weight: g typ.)

? FOR RELIABILITY GUIDANCE, PLEASE REFER TO THE APPLICATION NOTES AND COMMENTS (17).

24 bit ECC for each 1024 bytes is required.