TC74VHC138F_V01中文資料東芝數(shù)據(jù)手冊PDF規(guī)格書

The TC74VHC138 is an advanced high speed CMOS 3-to-8

DECODER fabricated with silicon gate C2MOS technology.

It achieves the high speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation.

When the device is enabled, 3 Binary Select inputs (A, B and

C) determine which one of the outputs (TO-Y7) will go low.

When enable input G1 is held low or either G2A or G2B is

held high, decoding function is inhibited and all outputs go high.

G1, G2A, and G2B inputs are provided to ease cascade

connection and for use as an address decoder for memory systems.

An input protection circuit ensures that 0 to 7V can be

applied to the input pins without regard to the supply

voltage. This device can be used to interface 5V to 3V

systems and two supply systems such as battery back up.

This circuit prevents device destruction due to mismatched

supply and input voltages.

FEATURES:

? High Speed...

? Low Power Dissipation………………..

High Noise Immunity

? Power Down Protection is provided on all inputs.

Balanced Propagation Delays tpLH=tpHL

Wide Operating Voltage Range....Vcc (opr) = 2V~5.5V

? Pin and Function Compatible with 74ALS138

tpd 5./ns(typ.) at Vcc=5V

Icc-4A(Max.) at Ta -25°C

?VNIH=VNIL = 28 Vcc (Min.)