TC74VHC9164FK中文資料東芝數(shù)據(jù)手冊PDF規(guī)格書

The TC74VHC9164 is an ultra-high-speed 8-Bit Shift Register

fabricated using silicon-gate CMOS technology. The

TC74VHC9164 combines low power consumption of CMOS with

Schottky TTL speeds.

The TC74VHC9164 has parallel data inputs/outputs, a serial

input and a serial output. It converts parallel data into serial data

or vice versa.

When P/S CONT is Low, Q/D1 to Q/D8 are configured as

parallel data outputs. At this time, the SI input is serially loaded on

the rising edges of CK and unloaded from the Q/D1 to Q/D8

outputs in parallel. When

CLR/LOAD

input is Low, all flip-flops are

asynchronously reset, irrespective of the CK state.

When P/S CONT is High, Q/D1 to Q/D8 are configured as

parallel data inputs. At this time, when

CLR/LOAD

is Low, Q/D1 to

Q/D8 latch data in parallel asynchronously from the CK input.

All the inputs have hysteresis between the positive-going and

negative-going thresholds. Thus the TC74VHC9164 is capable of

squaring up transitions of slowly changing input signals and

provides an improved noise immunity.

Additionally, all the inputs have a newly developed protection

circuit without a diode returned to VCC. This enables the inputs

to be tolerant of up to 5.5 volts even when power supply is down.

The input power-down protection capability makes the

TC74VHC9164 ideal for a wide range of applications, such as

interfacing between different voltages, voltage translation from 5

V to 3 V and battery back-up circuits.

Features

? High speed: fmax ? 149 MHz (typ.) at VCC ? 5 V

? Low power dissipation: ICC ? 4 ?A (max) at Ta ? 25°C

? Power down protection is provided on all inputs.

? Balanced propagation delays: tpLH

?

?

tpHL

? Wide operating voltage range: VCC (opr) ? 2 to 5.5 V