TC7MPN3125FTG中文資料東芝數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Low Voltage/Low Power 2-Bit × 2 Dual Supply Bus Transceiver

The TC7MPN3125FTG is a dual supply, advanced high-speed CMOS 4-bit dual supply voltage interface bus transceiver fabricated with silicon gate CMOS technology.

Features

? Bidirectional interface between 1.2-V and 1.8-V, 1.2-V and 2.5-V, 1.2-V and 3.3-V, 1.5-V and 2.5-V, 1.5-V and 3.3-V, 1.8-V and 2.5-V, 1.8-V and 3.3-V or 2.5-V and 3.3-V buses.

? High-speed operation: tpd = 13.7 ns (max) (VCCA = 2.5 ± 0.2 V, VCCB = 3.3 ± 0.3 V)

tpd = 14.8 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 3.3 ± 0.3 V)

tpd = 16.0 ns (max) (VCCA = 1.5 ± 0.1 V, VCCB = 3.3 ± 0.3 V)

tpd = 61 ns (max) (VCCA = 1.2 ± 0.1 V, VCCB = 3.3 ± 0.3 V)

tpd = 18.5 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 2.5 ± 0.2 V)

tpd = 19.7 ns (max) (VCCA = 1.5 ± 0.15 V, VCCB = 2.5 ± 0.2 V)

tpd = 60 ns (max) (VCCA = 1.2 ± 0.15 V, VCCB = 2.5 ± 0.2 V)

tpd = 58 ns (max) (VCCA = 1.2 ± 0.1 V, VCCB = 1.8 ± 0.15 V)

? Output current: IOHB/IOLB = ±3 mA (min) (VCCB = 3.0 V)

IOHB/IOLB = ±2 mA (min) (VCCB = 2.3 V)

IOHB/IOLB = ±0.5 mA (min) (VCCB = 1.65 V)

IOHA/IOLA = ±9 mA (min) (VCCA = 2.3 V)

IOHA/IOLA = ±3 mA (min) (VCCA = 1.65 V)

IOHA/IOLA = ±1 mA (min) (VCCA = 1.4 V)

? Latch-up performance: ±300 mA

? ESD performance: Machine model ≥ ±200 V

Human body model ≥ ±2000 V

? Ultra-small package: VQON16

? Low current consumption: Using the new circuit significantly reduces current consumption when OE = “H”.

Suitable for battery-driven applications such as PDAs and cellular phones.

? Floating A-bus and B-bus are permitted. (when OE = “H”)

3.6-V tolerant function and power-down protection provided on all inputs and outputs.