TPIM003中文資料TEWS數(shù)據(jù)手冊PDF規(guī)格書

Application Information

The TPMC634 is a standard single-width PMC module providing a user configurable Xilinx XC6SLX25 Spartan-6 FPGA.

The TPMC634-10R provides 64 ESD-protected TTL lines using TTL compatible buffers. The TPMC634-11R provides 32 differential I/O lines using ESD-protected EIA-422 / EIA-485 compatible line transceivers. The TPMC634-12R provides a mix of 16 differential EIA-422 / EIA-485 I/O lines and 32 TTL I/O lines. The TPMC634-13R provides 32 differential I/O lines using M-LVDS line transceivers. The TPMC634-14R provides a mix of 16 differential M-LVDS I/O lines and 32 TTL I/O lines.

All I/O lines are individually programmable as input or output. The receivers are always enabled. This allows reading the state of each I/O line at any time (monitoring I/O lines configured as outputs).

Each TTL I/O line has an on-board pull resistor to a common/shared reference. The pull resistor reference is configurable by an on-board rotary switch to 3.3V, 5V or GND. The differential I/O lines have on-board termination resistors.

The User FPGA is auto-configurable by an on-board serial SPI Flash. Both the User FPGA and the SPI flash for User FPGA configuration are in-system-programmable via the PCI bus. An on-board JTAG header provides access to the user FPGA JTAG port.

PCI configuration space parameters are configurable by an on-board serial EEPROM.