TPS7H1111-SEP中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

1 Features

? Total ionizing dose (TID) characterized

– Radiation hardness assurance (RHA)

availability of 100 krad(Si) or 50 krad(Si)

? Single-event effects (SEE) characterized

– Single-event latchup (SEL), single-event

burnout (SEB), and single-event gate rupture

(SEGR) immune up to linear energy transfer

(LET) = 75 MeV-cm2/mg

– Single-event functional interrupt (SEFI) and

single-event transient (SET) characterized up to

LET = 75 MeV-cm2/mg

? Ultra-Low Noise (10 Hz – 100 kHz):

– 1.71 μVRMS (typ)

? High power-supply rejection ratio, PSRR (typ):

– 109 dB at 1 kHz

– 71 dB at 100 kHz

– 66 dB at 1 MHz

? Input voltage range from 0.85 V to 7 V

? Bias supply of 2.2 V to 14 V to minimize power

dissipation

? Output voltage as low as 0.4 V

? Up to 1.5-A output current

? Excellent output accuracy over line and load:

– +1.1 / –1.3 across temperature

– +0.9 / –0.7 at 25°C

? Low-dropout: 215 mV (typ) at 1.5 A

? Programmable soft start control (SS_SET)

? Open-drain power good (PG) indicator

? Configurable power good threshold (FB_PG)

? Exposed control loop with the external

compensation STAB pin

? Internal current limit with configurable behavior

? Current sharing to allow operation of up to 2.9-A

? Military (–55°C to 125°C) temperature range

2 Applications

? Satellite electrical power system (EPS)

? Power for high-speed and high-accuracy circuits

– Data Converters: ADCs and DACs (analog-todigital

and digital-to-analog converters)

– VCOs (voltage controlled oscillators)

– PLLs (phase-lock-loops)

– SerDes (serializer and deserializers)

– Imaging sensors

? Accurate supply for FPGAs (field programmable

gate arrays) and DSPs (digital signal processors)

? Radiation-hardened ultra-clean analog supply for

space constrained areas

3 Description

The TPS7H1111 is an ultra-low noise, high PSRR, low

dropout linear regulator (LDO) optimized for powering

RF (radio frequency) devices in a space environment.

It is capable of sourcing up to 1.5 A over a 0.85-V to

7-V input range with a 2.2-V to 14-V bias supply.

The high performance of the device limits powersupply

generated phase noise and clock jitter, making

this device ideal for powering high-performance

ADCs, DACs, VCOs, PLLs, SerDes, and other RF

components in satellites. For digital loads (such as

FPGAs and DSPs) requiring low voltage operation,

the exceptional accuracy and excellent transient

performance ensure optimal system performance.

A standard microcircuit drawing (SMD) is available

for the QML variants, 5962R21203. A vendor item

drawing (VID) is available for the SEP variant,

V62/23602.