TXV0108-Q1中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

1 Features

? AEC-Q100 qualified for automotive applications

? Integrated damping output resistor

? Pin compatible with SN74AVC8T245

? Direction controlled voltage level shifter and buffer

for general and skew sensitive applications

? Meets RGMII 2.0 standard timing specifications:

– < 750 ps rise and fall time

– < 400 ps channel to channel skew

– < ± 5 duty cycle distortion

? Fully configurable symmetric dual-rail design

allows each port to operate from 1.65 V to 3.6 V

? Supports up to 320-Mbps for 1.65 V to 3.6 V

– 250-Mbps maximum to meet RGMII timing

specs

? High drive strength (up to 12 mA at 3.6 V)

? Low power consumption:

– 10-μA maximum (25°C)

– 20-μA maximum (–40°C to 125°C)

? VCC isolation and VCC disconnect (Ioff-float) feature

– If either VCC supply is < 100 mV or

disconnected, then all I/Os get pulled-down and

then become high-impedance

? Ioff supports partial-power-down mode operation

? Operating temperature from –40°C to +125°C

? Latch-up performance exceeds 100 mA per JESD

78, Class II

? ESD protection exceeds JESD 22:

– 2000-V Human-Body Model

– 1000-V Charged-Device Model

2 Applications

? Medium or short range radar

? ADAS domain controller

? HVAC controller design

? Machine vision camera

? Rack server motherboard

? IP telephone

3 Description

The TXV0108-Q1 is a 8-bit, dual-supply direction

controlled low-skew voltage translation device. This

device can be used for buffering or redriving, voltage

translation and power up isolation on transmitting

skew sensitive interface, such as RGMII signals

between MAC and PHY. Ax pins and control pins

(DIR, OE) are referenced to VCCA logic levels, and

Bx pins are referenced to VCCB logic levels. This

device has an improved channel-to-channel skew,

duty cycle distortion and symmetric rise or fall timing

for applications requiring strict timing conditions.

This device is fully specified for partial-power-down

applications using Ioff. The Ioff circuitry disables the

outputs, thus preventing damaging current backflow

through the device when it is powered down.

The VCC isolation feature is designed so that if either

VCC supply is at or near 0 V both ports will switch to

a high-impedance state. This feature enables power

isolation for communications across multiple MACs

and PHYs, and is beneficial in situations where MACs

and PHYs are powered up asynchronously preventing

current backflow between devices.

A high on DIR allows data transmission from A to B

while a low on DIR allows data transmission from B to

A when OE is set to low. When OE is set to high, both

Ax and Bx pins will be forced into a high-impedance

state. See Device Functional Modes for a summary of

the operation of the control logic.