U62H256AS2K55G1中文資料ZMD數(shù)據(jù)手冊(cè)PDF規(guī)格書

Description

The U62H256A is a static RAM manufactured using a CMOS proess technology with the following

operating modes: Read - Standby

Write - Data Retention

The memory array is based on a 6-transistor cell. The circuit is activated by the falling edge of E. The address and ontrol inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. In a Read cycle, the data outputs are activated by the alling edge of G, afterwards the data word will be available at the outputs DQ0-DQ7. After the address change, the data outputs go High-Z until the new information is available. The data outputs have

no preferred state. The Read cycle is finished by the falling edge of W, or by the rising edge of E, respectively.

Data retention is guaranteed down to 2 V. With the exception of E, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required.

Features

!32768 x 8 bit static CMOS RAM

!35 and 55 ns Access Time

!Common data inputs and data outputs

!Three-state outputs

!Typ. operating supply current

35 ns: 45 mA

55 ns: 30 mA

!Standby current < 50 μA at 125 °C

!TTL/CMOS-compatible

!Power supply voltage 5 V

!Operating temperature range

-40 °C to 85 °C

-40 °C to 125 °C

!QS 9000 Quality Standard

!ESD protection > 2000 V

(MIL STD 883C M3015.7)

!Latch-up immunity >100 mA

!Package: SOP28 (300/330 mil)