UPD160010中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

? Differential interface: CLK, gray scale data,

? CMOS interface: STHR(L), R,/L, STB, SB, POL, Osel, Vsel1, Vsel2, SRC, ORC, RxBIAS1, RxBIAS2

? 384/360 outputs (Osel)

? Capable of outputting 256 values by means of 10-by-2 external power modules (20 units) and a D/A converter

? Logic power supply voltage (VDD1): 2.7 to 3.6V

? Driver power supply voltage (VDD2): 10.0 to 16.5V

? High-speed data transfer: fCLK = 190 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.7 V)

? Output dynamic range: VSS2 + 0.2 V to VDD2 ? 0.2 V

? Apply for dot-line inversion, n-line inversion

? Output voltage polarity inversion function (POL)