UPD16772A中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

· CMOS level input (2.3 to 3.6 V)

· 480 outputs

· Input of 6 bits (gradation data) by 6 dots

· Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (RDAC)

· Output dynamic range : VSS2 + 0.1 V to VDD2 – 0.1 V

· High-speed data transfer : fCLK = 45 MHz (internal data transfer speed when operating at VDD1 = 2.3 V)

· Apply for dot-line inversion, n-line inversion and column line inversion

· Output voltage polarity inversion function (POL)

· Display data inversion function (POL21/22)

· Current consumption reduction function (LPC, Bcont)

· Logic power supply voltage (VDD1) : 2.3 to 3.6 V

· Driver power supply voltage (VDD2) : 8.5 V ± 0.5 V