UPD178018A中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

? Internal high-capacity ROM and RAM

? Instruction Cycle: 0.44 ms (4.5-MHz crystal oscillator used)

? Large array of on-chip peripheral hardware

General-purpose input/output port, A/D converter, serial interface, timer, frequency counter, power-ON clear circuits.

? On-chip hardware for a PLL frequency synthesizer.

Dual modulus pre-scaler, programmable divider, phase comparator, charge pump.

? Vector interrupt sources: 17

? Supply Voltage: VDD = 4.5 to 5.5 V (during PLL operation)

VDD = 3.5 to 5.5 V (during CPU operation, when the system clock is fX/2 or lower)

VDD = 4.5 to 5.5 V (during CPU operation, when the system clock is fX)