UPD30102GM-54-8EV中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

? Employs 64-bit MIPS architecture

? Conforms to MIPS III instruction set (deleting FPU,

LL, SC instructions)

? Optimized 5-stage pipeline

? Supports high-speed product-sum operation

instructions

? Supports four types of operating modes, enabling more

effective power-consumption management

? Internal operating frequency: 54 MHz

? On-chip clock generator

? Address space physical : 32 bits

virtual : 40 bits

Integrates 32 double entry TLBs

? High-capacity instruction/data fields separated cache

memory

Instruction field: 4 Kbytes

Data field : 1 Kbyte