UPD488448FF-C80-45-DQ1中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Description

The Direct Rambus DRAM (Direct RDRAM?) is a general purpose high-performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required.

The μPD488448 is 128M-bit Direct Rambus DRAM (RDRAM?), organized as 8M words by 16 bits. The use of Rambus Signaling Level (RSL) technology permits 600 MHz to 800 MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10 ns per sixteen bytes).

The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95 bus efficiency. The Direct RDRAM’s thirty-two banks support up to four simultaneous transactions. System oriented features for mobile, graphics and large memory systems include power management, byte masking.

The μPD488448 is offered in a CSP horizontal package suitable for desktop as well as low-profile add-in card and mobile applications. Direct RDRAMs operate from a 2.5 volt supply.

Features

? Highest sustained bandwidth per DRAM device

- 1.6 GB/s sustained data transfer rate

- Separate control and data buses for maximized efficiency

- Separate row and column control buses for easy scheduling and highest performance

- 32 banks: four transactions can take place simultaneously at full bandwidth data rates

? Low latency features

- Write buffer to reduce read latency

- 3 precharge mechanisms for controller flexibility

- Interleaved transactions

? Advanced power management:

- Multiple low power states allows flexibility in power consumption versus time to transition to active state

- Power-down self-refresh

? Overdrive current mode

? Organization: 1 Kbyte pages and 32 banks, x 16

? Uses Rambus Signaling Level (RSL) for up to 800 MHz operation

? Package : 62-pin TAPE FBGA (μBGA?) and 62-pin PLASTIC FBGA (D2BGA? (Die Dimension Ball Grid Array) )