UPD65949S1-P00-F6中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

? Direct connection to any MIPS R4x00 CPU with a 32-bit SysAD bus

? Direct connection to 32-bit 33 MHz PCI bus, conforming to Rev. 2.1

? Integrated PCI arbiter acting as PCI master or target

? Independent CPU and PCI input clocks

? Internal ‘cache’ for local memory locations provides greatly enhanced PCI transfer performance for

device controllers which are PCI bus initiators

? PCI/local-memory copier for applications requiring bulk data transport

? 16-bit local I/O bus for local ROM and ‘slow’ peripherals