UPD703039YGM中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

DESCRIPTION

The μPD703039, 703039Y, 703040, 703040Y, 703041, and 703041Y (collectively known as the V850/SV1) are products in the low-power series of V850 FamilyTM products, which are NEC’s single-chip microcontrollers for real time control.

The V850/SV1 employs the CPU core of the V850 Family, and has on-chip peripheral functions such as large capacity ROM/RAM, a multi-function timer/counter, serial interface, A/D converter, DMA controller, PWM, and a Vsync/Hsync separation circuit.

The V850/SV1 not only realizes the low power consumption necessary for applications such as camcorders, but also extremely high cost performance.

FEATURES

● Number of instructions: 74

● Minimum instruction execution time:

62.5 ns (@ 16 MHz operation with main system clock)

30.5 μs (@ 32.768 kHz operation with subsystem clock)

● General-purpose registers: 32 bits × 32 registers

● Instruction set (signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions, load/store instructions)

● Memory space:

16 MB linear address space

Memory block allocation function: 2 MB per block

? External bus: 16-bit multiplexed bus

? Internal memory:

μPD703039, 703039Y

(ROM: 256 KB, RAM: 8 KB)

μPD703040, 703040Y

(ROM: 256 KB, RAM: 16 KB)

μPD703041, 703041Y

(ROM: 192 KB, RAM: 8 KB)

● I/O lines Total: 151

● 10-bit resolution A/D converter: 16 channels

● Timer/counter

24-bit: 2 channels, 16-bit: 2 channels

8-bit: 8 channels

● Watch timer: 1 channel

● Watchdog timer: 1 channel

● DMA controller: 6 channels

● Interrupts and exceptions

Non-maskable interrupt: 2 sources

Maskable interrupt

: μPD703039, 703040, 703041 (51 sources)

: μPD703039Y, 703040Y, 703041Y (52 sources)

Software exception: 32 sources

Exception trap: 1 source

● Serial interface (SIO)

Asynchronous serial interface (UART)

Clocked serial interface (CSI)

3-wire variable length serial interface (CSI4)

I2C bus interface (I2C) (μPD703039Y, 703040Y, 703041Y)

● RTP: 8 bits × 2 channels or 4 bits × 4 channels