UPD70320GJ-5BG中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

? Internal 16-bit architecture and external 8-bit data bus

? Compatible with mPD70108/70116 (in native mode) on software level (some instructions added)

? Minimum instruction cycle : 400 ns/5 MHz (mPD70320)

250 ns/8 MHz (mPD70320-8)

? On-chip RAM : 256 words ′ 8 bits

? Input port (port T) with comparator : 8 bits

? I/O lines (input port : 4 bits, input/output port : 20 bits)

? Serial interface (internal dedicated baud rate generator) : 2 channels

Asynchronous mode and I/O interface mode

? Interrupt controller

? Programmable priority (8 levels)

? Vectored interrupt function

? Register bank switching function

? Macro service function

? DRAM and pseudo SRAM refreshing functions

? DMA controller : 2 channels

? 16-bit timer : 2 channels

? Time base counter

? On-chip clock generator

? Programmable wait function

? Standby function (STOP/HALT)