UPD70325中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

? Software compatible with V25

? Software compatible with mPD70108/70116 (in native mode) (some instructions added)

? Internal 16-bit architecture and external 8-bit data bus

? 3-stage pipeline method

? Minimum instruction cycle : 250 ns/8 MHz (external 16 MHz)

: 200 ns/10 MHz (external 20 MHz)

? Memory space 1 Mbyte

? On-chip RAM : 256 words ′ 8 bits

? Register bank (memory mapped method) : 8 banks

? Input port (port T) with comparator : 8 bits

? I/O lines (input port : 4 bits, input/output ports : 20 bits)

? Serial interface : 2 channels

? Internal dedicated baud rate generator

? Asynchronous mode and I/O interface mode

? Interrupt controller

? Programmable priority (8 levels)

? 3 types of interrupt response method

Vectored interrupt function, register bank switching function, macro service function

? DRAM and pseudo SRAM refreshing function

? DMA controller : 2 channels

? 4 types of DMA transfer mode

? Transfer rate Maximum 4 Mbytes/second (when stop control is not executed by DMARQ pin in demand release mode)

Maximum 2 Mbytes/second (when stop control is executed by DMARQ pin in demand release

mode, or burst mode)

? Address pointer (linear) : 20 bits

? Terminal counter : 16 bits

? 16-bit timer : 2 channels

? Time base counter (20 bits) : 1 channel

? On-chip clock generator

? Programmable wait function

? Standby function (STOP, HALT)