UPD720120中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

? Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps)

? 16 bits backend Interface to SIE

? (Micro) SOF detection for High-/Full-speed operation

? One high-speed transceiver / receiver with full-speed transceiver / receiver

? High-speed or Full-speed packet protocol sequencer

? Start / End of packet detection

? NRZI encoding / decoding

? Stuffed bit insertion / recognition and stripping

? CRC checker and generation ( 5 bits CRC for Token packet and 16bits CRC for Data packet)

? Serial to 16 bits parallel conversion for data reception and 16 bits parallel to serial conversion for data

transmission

? Automatic chirp assertion and full-/high-speed mode change

? USB Reset, Suspend and Resume signaling detection

? Supports remote wakeup functionality

? Supports set feature (TEST_MODE) functionality

? System Clock is generated by 30 MHz X’tal

? Several Clock Outputs (30 MHz, 60 MHz) are provided for backend interface.

? 3.3 V power supply