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UPD78323GJ-5BJ中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

UPD78323GJ-5BJ
廠商型號(hào)

UPD78323GJ-5BJ

功能描述

MOS INTEGRATED CIRCUIT

文件大小

632.69 Kbytes

頁(yè)面數(shù)量

88 頁(yè)

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-2-10 17:21:00

UPD78323GJ-5BJ規(guī)格書詳情

FEATURES

· Internal 16-bit architecture and external 8-bit data bus

· High-speed processing by pipeline control and instruction prefetch

? Minimum instruction execution time: 250 ns (with 16 MHz external clock in operation)

· Instruction set suitable for control operations (mPD78312 upward compatible)

? Multiply/divide instructions (16 bits ′ 16 bits, 32 bits ? 16 bits)

? Bit manipulation instruction

? String instruction, etc.

· On-chip high-function interrupt controller

? 3-level priority specifiable

? 3-type interrupt processing mode selectable

(Vectored interrupt function, context switching function, and macro service function)

· Variety of peripheral hardware

? Realtime pulse unit

? 8-channel, 10-bit A/D converter

? Watchdog timer

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