UPD78F9872GB-8ET中文資料瑞薩數據手冊PDF規(guī)格書

FEATURES

? Pin compatible with mask ROM version (except VPP pin)

? Internal ROM and RAM

? Flash memory: 16 KB

? Internal high-speed RAM: 512 bytes

? VFD display RAM: 96 bytes

? Minimum instruction execution time can be changed from high-speed (0.4 ms: Main system clock 5.0-MHz

operation) to ultra-low speed (122 ms: Subsystem clock 32.768-kHz operation)

? I/O ports: 33

? Timers: 5 channels

? 8-bit remote control: 1 channel

? 8-bit timer/event counter: 2 channels

? Watch timer: 1 channel

? Watchdog timer: 1 channel

? Serial interface: 1 channel

? VFD controller/driver: Total of display outputs: 25

? Power supply voltage : VDD = 2.7 to 5.5 V (in normal operation)

: VDD = 4.5 to 5.5 V (when VFD is operating)