V53C16258SLT50中文資料茂矽電子數(shù)據(jù)手冊PDF規(guī)格書

Description

The V53C16258L is a 262,144 x 16 bit high-performance CMOS dynamic random access memory. The V53C16258L offers Page mode with Extended Data Output. An address, CAS and RAS input capacitances are reduced to one quarter when the x4 DRAM is used to construct the same memory density. The V53C16258L has symmetric address and accepts 512 cycle 8ms interval.

All inputs are TTL compatible. EDO Page Mode operation allows random access up to 512 x 16 bits, within a page, with cycle times as short as 15ns.

The V53C16258L is ideally suited for a wide variety of high performance portable computer systems and peripheral applications.

Features

■ 256K x 16-bit organization

■ EDO Page Mode for a sustained data rate of 71 MHz

■ RAS access time: 35, 40, 45, 50 ns

■ Dual CAS Inputs

■ Low power dissipation

■ Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh, and Self Refresh

■ Optional Self Refresh (V53C16258SL)

■ Refresh Interval: Standard: 512 cycles/8ms

■ Available in 40-pin 400 mil SOJ and 40/44L-pin 400 mil TSOP-II packages

■ Single +3.3V ±0.3V Power Supply

■ TTL Interface