V55C2128164VB中文資料茂矽電子數(shù)據(jù)手冊(cè)PDF規(guī)格書

Description

The V55C2128164V(T/B) is a four bank Synchronous DRAM organized as 4 banks x 2Mbit x 16. The V55C2128164V(T/B) achieves high speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock

All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166 MHz is possible depending on burst length, CAS latency and speed grade of the device.

Features

■ 4 banks x 2Mbit x 16 organization

■ High speed data transfer rates up to 166 MHz

■ Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge

■ Single Pulsed RAS Interface

■ Data Mask for Read/Write Control

■ Four Banks controlled by BA0 & BA1

■ Programmable CAS Latency:1, 2, 3

■ Programmable Wrap Sequence: Sequential or Interleave

■ Programmable Burst Length:

1, 2, 4, 8, Full page for Sequential Type

1, 2, 4, 8 for Interleave Type

■ Multiple Burst Read with Single Write Operation

■ Automatic and Controlled Precharge Command

■ Random Column Address every CLK (1-N Rule)

■ Power Down Mode and Clock Suspend Mode

■ Deep Power Mode

■ Auto Refresh and Self Refresh

■ Refresh Interval: 4096 cycles/64 ms

■ Available in 54-ball FBGA, with 9x6 ball array with 3 depupulated rows, 9x8 mm and 54 pin TSOP II

■ VDD=2.5V, VDDQ=1.8V

■ Programmable Power Reduction Feature by partial array activation during Self-Refresh

■ Operating Temperature Range

Commercial (0°C to 70°C)

Extended (-25°C to +85°C)