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V62/23630-01XE中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書

V62/23630-01XE
廠商型號(hào)

V62/23630-01XE

功能描述

SN54SC4T86-SEP Radiation Tolerant, Quadruple 2-Input Exclusive-OR Gates

絲印標(biāo)識(shí)

SC86SEP

封裝外殼

TSSOP

文件大小

1.05182 Mbytes

頁(yè)面數(shù)量

24 頁(yè)

生產(chǎn)廠商 Texas Instruments
企業(yè)簡(jiǎn)稱

TI1德州儀器

中文名稱

德州儀器官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-2-10 14:27:00

V62/23630-01XE規(guī)格書詳情

1 Features

? Vendor item drawing available, VID

V62/23630-01XE

? Total ionizing dose characterized at 30 krad (Si)

– Total ionizing dose radiation lot acceptance

testing (TID RLAT) for every wafer lot to 30

krad (Si)

? Single-event effects (SEE) characterized:

– Single event latch-up (SEL) immune to linear

energy transfer (LET) = 43 MeV-cm2 /mg

– Single event transient (SET) characterized to

43 MeV-cm2 /mg

? Wide operating range of 1.2 V to 5.5 V

? Single-supply translating gates at 5/3.3/2.5/1.8/1.2

V VCC

– TTL compatible inputs:

? Up translation:

– 1.8-V – Inputs from 1.2 V

– 2.5-V – Inputs from 1.8 V

– 3.3-V – Inputs from 1.8 V, 2.5 V

– 5.0-V – Inputs from 2.5 V, 3.3 V

? Down translation:

– 1.2-V – Inputs from 1.8 V, 2.5 V, 3.3 V,

5.0 V

– 1.8-V – Inputs from 2.5 V, 3.3 V, 5.0 V

– 2.5-V – Inputs from 3.3 V, 5.0 V

– 3.3-V – Inputs from 5.0 V

? 5.5 V tolerant input pins

? Output drive up to 25 mA AT 5-V

? Latch-up performance exceeds 250 mA per

JESD 17

? Space enhanced plastic (SEP)

– Controlled baseline

– Gold bondwire

– NiPdAu lead finish

– One assembly and test site

– One fabrication site

– Military (–55°C to 125°C) temperature range

– Extended product life cycle

– Product traceability

– Meets NASAs ASTM E595 outgassing

specification

2 Applications

? Enable or disable a digital signal

? Controlling an indicator LED

? Translation between communication modules and

system controllers

3 Description

The SN54SC4T86-SEP contains four independent

2-input XOR Gates with Schmitt-trigger inputs

with extended voltage operation to allow for level

translation. Each gate performs the Boolean function

Y = A ⊕ B in positive logic. The output level is

referenced to the supply voltage (VCC) and supports

1.2-V, 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to

support up translation for lower voltage CMOS inputs

(for example 1.2 V input to 1.8 V output or 1.8 V input

to 3.3 V output). Additionally, the 5-V tolerant input

pins enable down translation (for example 3.3 V to 2.5

V output).

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