V850E1中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

GENERAL

Real-time control systems are used in a wide range of applications, including:

? office equipment such as HDDs (Hard Disk Drives), PPCs (Plain Paper Copiers), printers, and facsimiles,

? automobile electronics such as engine control systems and ABSs (Antilock Braking Systems), and

? factory automation equipment such as NC (Numerical Control) machine tools and various controllers.

The great majority of these systems conventionally employ 8-bit or 16-bit microcontrollers. However, the performance level of these microcontrollers has become inadequate in recent years as control operations have risen in complexity, leading to the development of increasingly complicated instruction sets and hardware design. As a result, the need has arisen for a new generation of microcontrollers operable at much higher frequencies to achieve an acceptable level of performance under today’s more demanding requirements.

The V850 Series of microcontrollers was developed to satisfy this need. This series uses RISC architecture that can provide maximum performance with simpler hardware, allowing users to obtain a performance approximately 15 times higher than that of the existing 78K/III Series and 78K/IV Series of CISC single-chip microcontrollers at a lower total cost.

In addition to the basic instructions of conventional RISC CPUs, the V850 Series is provided with special instructions such as saturation, bit manipulation, and multiply/divide (executed by a hardware multiplier) instructions, which are especially suited to digital servo control systems. Moreover, instruction formats are designed for maximum compiler coding efficiency, allowing the reduction of object code sizes.

The V850E1 CPU is a 32-bit RISC CPU core for ASIC, newly developed as the CPU core central to system LSI in the current age of system-on-a-chip. This core includes not only the control functions of the V850 CPU, the CPU core incorporated in the V850 Series, but also supports data processing through its enhanced external bus interface performance, and the addition of features such as C language switch statement processing, table lookup branching, stack frame creation/deletion, data conversion, and other high-level language supporting instructions.

In addition, because the instruction codes are upwardly compatible with the V850 CPU at the object code level, the software resources of systems that incorporate the V850 CPU can be used unchanged.

Features

(1) High-performance 32-bit architecture for embedded control

? Number of instructions: 83

? 32-bit general-purpose registers: 32

? Load/store instructions in long/short format

? 3-operand instruction

? 5-stage pipeline of 1 clock cycle per stage

? Hardware interlock on register/flag hazards

? Memory space

Program space: 64 MB linear

Data space: 4 GB linear

(2) Special instructions

? Saturation operation instructions

? Bit manipulation instructions

? Multiply instructions (On-chip hardware multiplier executing multiplication in 1 clock)

16 bits × 16 bits → 32 bits

32 bits × 32 bits → 32 bits or 64 bits