W986408CH中文資料華邦電子數(shù)據(jù)手冊PDF規(guī)格書

General Description

W986408CH is a high speed synchronous dynamic random access memory (SDRAM) , organized as 2M words x 4 banks x 8 bits. Using pipelined architecture and 0.20um process technology, W986408CH delivers a data bandwidth of up to 133M ( - 75) bytes per second. To fully comply to the personal computer industrial standard, W986408CH is sorted into two speed grades: -75 and -8H. The -75 is compliant to the PC133 specitication, The -8H is compliant to the PC100/CL2 specification

Features

? 3.3V ± 0.3V power supply

? Up to 133MHz clock frequency

? 2,097,152 words x 4 banks x 8 bits organization

? Auto Refresh and Self Refresh

? CAS latency: 2 and 3

? Burst Length: 1, 2, 4, 8 , and full page

? Burst read, Single Writes Mode

? Byte data controlled by DQM

? Power-Down Mode

? Auto-Precharge and controlled precharge

? 4k refresh cycles / 64ms

? Interface: LVTTL

? Package: TSOP II 54 pin, 400 mil - 0.80