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WC32P040-XQ4M中文資料WEDC數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

WC32P040-XQ4M
廠(chǎng)商型號(hào)

WC32P040-XQ4M

功能描述

32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface

文件大小

726.71 Kbytes

頁(yè)面數(shù)量

23 頁(yè)

生產(chǎn)廠(chǎng)商 White Electronic Designs Corporation
企業(yè)簡(jiǎn)稱(chēng)

WEDC

中文名稱(chēng)

White Electronic Designs Corporation

原廠(chǎng)標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二

更新時(shí)間

2025-1-25 10:02:00

WC32P040-XQ4M規(guī)格書(shū)詳情

DESCRIPTION

The WC32P040 is a 68000-compatible, high-performance, 32-bit microprocessor. The WC32P040 is a virtual memory microprocessor employing multiple concurrent execution units and a highly intergrated architecture that provides very high performance in a monolithic HCMOS device. It has a 68030-compatible integer unit (IU) and two independent caches. The WC32P040 contains dual, independent, demand-paged memory management units (MMUs) for instruction and data stream accesses and independent, 4-Kbyte instruction and data caches. The WC32P040 has a 68881/68882-compatible fl oating-point unit (FPU).

68040 FEATURES

■ Selection of Processor Speeds: 25, 33MHz

■ Military Temperature Range: -55°C to +125°C

■ Packaging

? 179 pin Ceramic PGA (P4)

? 184 lead Ceramic Quad Flatpack, CQFP (Q4)

■ 6-Stage Pipeline, 68030-Compatible IU

■ 68881/68882-Compatible FPU

■ Independent Instruction and Data MMUs

■ Simultaneously Accessible, 4-Kbyte Physical Instruction Cache and 4-Kbyte Physical Data Cache

■ Low-Latency Bus Acceses for Reduced Cache Miss Penalty

■ Multimaster/Multiprocessor Support via Bus Snooping

■ Concurrent IU, FPU, MMU, and Bus Controller Operation Maximizes Throughput

■ 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface

■ User Object-Code Compatible with all Earlier 68000 Microprocessors

■ 4-GigaByte Direct Addressing Rang

產(chǎn)品屬性

  • 型號(hào):

    WC32P040-XQ4M

  • 制造商:

    WEDC

  • 制造商全稱(chēng):

    White Electronic Designs Corporation

  • 功能描述:

    32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface

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