WED2CG472512V-D2中文資料WEDC數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

DESCRIPTION

The WED2CG472512V is a Synchronous/Synchronous Burst SRAM, 84 position Dual Key; Double High DIMM (168 contacts) Module, organized as 4x512Kx72. The Module contains sixteen (16) Synchronous Burst RAM devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate.

FEATURES

■ 4x512Kx72 Synchronous, Synchronous Burst

■ Flow-Through Architecture

■ Linear and Sequential Burst Support via MODE pin

■ Clock Controlled Registered Module Enable (EM#)

■ Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#)

■ Clock Controlled Byte Write Mode Enable (BWE#)

■ Clock Controlled Byte Write Enables (BW1# - BW8#)

■ Clock Controlled Registered Address

■ Clock Controlled Registered Global Write (GW#)

■ Asynchronous Output Enable (G#)

■ Internally Self-Timed Write

■ Individual Bank Sleep Mode Enables (ZZ1, ZZ2, ZZ3, ZZ4)

■ Gold Lead Finish

■ 3.3V ± 10 Operation

■ Frequency(s): 100, 83, 67, 50MHz

■ Access Speed(s): tKHQV = 7.5, 9, 10, 12, 15ns

■ Common Data I/O

■ High Capacitance (30pF) Drive, at Rated Access Speed

■ Single Total Array Clock