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WEDPNF8M721V-1212BI中文資料ETC數(shù)據(jù)手冊PDF規(guī)格書

WEDPNF8M721V-1212BI
廠商型號(hào)

WEDPNF8M721V-1212BI

功能描述

8Mx72 Synchronous DRAM 8Mb Flash Mixed Module Multi-Chip Package

文件大小

1.27644 Mbytes

頁面數(shù)量

42

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中文名稱

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更新時(shí)間

2025-1-5 10:50:00

WEDPNF8M721V-1212BI規(guī)格書詳情

[White-Electronic]

FEATURES

■ Package:

? 275 Plastic Ball Grid Array (PBGA), 32mm x 25mm

■ Commercial, Industrial and Military Temperature Ranges

■ Weight:

? WEDPNF8M721V-XBX - 2.5 grams typical

SDRAM PERFORMANCE FEATURES

■ Organized as 8M x 72

■ High Frequency = 100, 125MHz

■ Single 3.3V ±0.3V power supply

■ Fully Synchronous; all signals registered on positive edge of system clock cycle

■ Internal pipelined operation; column address can be changed every clock cycle

■ Internal banks for hiding row access/precharge

■ Programmable Burst length 1,2,4,8 or full page

■ 4096 refresh cycles

FLASH PERFORMANCE FEATURES

■ User Configurable as 1Mx8 or 512Kx16

■ Access Times of 100, 120, 150ns

■ 3.3 Volt for Read and Write Operations

■ 1,000,000 Erase/Program Cycles

■ Sector Architecture

? One 16KByte, two 8KBytes, one 32KByte, and fif teen 64KBytes in byte mode

? One 8K word, two 4K words, one 16K word, and fifteen 32K word sectors in word mode.

? Any combination of sectors can be concurrently erased. Also supports full chip erase

■ Boot Code Sector Architecture (Bottom)

■ Embedded Erase and Program Algorithms

■ Erase Suspend/Resume

? Supports reading data from or programing data to a sector not being erased

BENEFITS

■ 42 SPACE SAVINGS

■ Reduced part count

■ Reduced I/O count

? 14 I/O Reduction

■ Suitable for hi-reliability applications

■ SDRAM Upgradeable to 16M x 72 density (contact factory for information)

■ Flash upgradeable to 2M x 8 (or 1M x 16 or 512K x 32) density

產(chǎn)品屬性

  • 型號(hào):

    WEDPNF8M721V-1212BI

  • 功能描述:

    8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package

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