XA-G30中文資料飛利浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書

FAMILY DESCRIPTION

The Philips Semiconductors XA (eXtended Architecture) family of 16-bit single-chip microcontrollers is powerful enough to easily handle the requirements of high performance embedded applications, yet inexpensive enough to compete in the market for high-volume, low-cost applications.

The XA architecture supports:

? Upward compatibility with the 80C51 architecture

? 16-bit fully static CPU with a 24-bit program and data address range

? Eight 16-bit CPU registers each capable of performing all arithmetic and logic operations as well as acting as memory pointers. Operations may also be performed directly to memory.

? Both 8-bit and 16-bit CPU registers, each capable of performing all arithmetic and logic operations.

? An enhanced instruction set that includes bit intensive logic operations and fast signed or unsigned 16 × 16 multiply and 32 / 16 divide

? Instruction set tailored for high level language support

? Multi-tasking and real-time executives that include up to 32 vectored interrupts, 16 software traps, segmented data memory, and banked registers to support context switching

? Low power operation, which is intrinsic to the XA architecture, includes power-down and idle modes.

SPECIFIC FEATURES OF THE XA-G30

? 20-bit address range, 1 megabyte each program and data space. (Note that the XA architecture supports up to 24 bit addresses.)

? 2.7 V to 5.5 V operation

? 512 bytes of on-chip data RAM

? Three counter/timers with enhanced features (equivalent to 80C51 T0, T1, and T2)

? Watchdog timer

? Two enhanced UARTs

? Four 8-bit I/O ports with 4 programmable output configurations

? 44-pin PLCC and 44-pin LQFP packages