XC56307GC100C中文資料恩智浦數據手冊PDF規(guī)格書

FEATURES

High-Performance DSP56300 Core

￥ 100 million instructions per second (MIPS) with a 100 MHz clock at 2.5 V core and

3.3 V I/O

￥ Object code compatible with the DSP56000 core

￥ Highly parallel instruction set

￥ Data arithmetic logic unit (ALU)

D Fully pipelined 24 x 24-bit parallel multiplier-accumulator

D 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and

parsing)

D Conditional ALU instructions

D 24-bit or 16-bit arithmetic support under software control

￥ Program control unit (PCU)

D Position independent code (PIC) support

D Addressing modes optimized for DSP applications (including immediate offsets)

D On-chip instruction cache controller

D On-chip memory-expandable hardware stack

D Nested hardware DO loops

D Fast auto-return interrupts

￥ Direct memory access (DMA)

D Six DMA channels supporting internal and external accesses

D One-, two-, and three- dimensional transfers (including circular buffering)

D End-of-block-transfer interrupts

D Triggering from interrupt lines and all peripherals

￥ Phase-locked loop (PLL)

D Allows change of low power divide factor (DF) without loss of lock

D Output clock with skew elimination

￥ Hardware debugging support

D On-Chip Emulation (OnCE

?

) module

D Joint test action group (JTAG) test access port (TAP)

D Address trace mode reflects internal Program RAM accesses at the external port

APPLICATIONS

The DSP56307 is intended for applications requiring a large amount of on-chip memory, such as

wireless infrastructure applications. The EFCOP may be used to accelerate general filtering

applications, such as echo-cancellation applications, correlation, and general purpose

convolution-based algorithms.