XRT84L38中文資料艾科嘉數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The XRT84L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framing controller. The XRT84L38 contains an integrated DS1/E1/J1 framer which provides DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications. Each framer has its own framing synchronizer and transmit-receive slip buffers, and can be independently enabled or disabled as required and can be configured to frame to the common DS1/E1/J1 signal formats.

FEATURES

? Eight independent, full duplex DS1 Tx and Rx Framers

? Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz asynchronous back plane connections with jitter and wander attenuation

? Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 4-channel multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus

? Programmable output clocks for Fractional T1/E1/J1

? Supports Channel Associated Signaling (CAS)

? Supports Common Channel Signalling (CCS)

? Supports ISDN Primary Rate Interface (ISDN PRI) signaling

? Extracts and inserts robbed bit signaling (RBS)

? 3 independent HDLC Controllers for Receive and Transmit on a per channel basis

? Each HDLC controller contains two 96-BYTE buffers

? Timeslot assignable HDLC

? V5.1 and V5.2 Interface

? 8-bit Intel/Motorola μP and MIPS Power PC interfaces for configuration, control and status monitoring

? Parallel search algorithm for fast frame synchronization

? Wide choice of T1 framing structures: D4, ESF, SLC?96, TIDM and N-Frame (non-framing)

? Direct access to D and E channels for fast transmission of data link information

? PRBS and QRSS generation and detection

? Programmable Interrupt output pin

? Supports programmed I/O, Burst and DMA modes of Read-Write access

? Each framer block encodes and decodes the T1/E1/J1 Frame serial data into and from the Single-rail or Dual-rail (B8ZS) format

? Dual or single rail line side digital PCM inputs

? Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms

? Detects OOF, LOF, LOS errors and COFA conditions

? Loopbacks: Local (LLB) and Line remote (LB)

? Facilitates Inverse Multiplexing for ATM

? Performance monitor with one second polling

? Boundary scan (IEEE 1149.1) JTAG test port

? Accepts external 8kHz Sync reference

? 3.3V CMOS operation with 5V tolerant inputs

? 388-pin BGA package with –40°C to +85°C operation

? Direct Interface to Exar’s XRT83L38 (Octal) LIU

APPLICATIONS

? High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems

? SONET/SDH terminal or Add/Drop multiplexers (ADMs)

? T1/E1/J1 add/drop multiplexers (MUX)

? Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1

? Digital Access Cross-connect System (DACs)

? Digital Cross-connect Systems (DCS)

? Frame Relay Switches and Access Devices (FRADS)

? ISDN Primary Rate Interfaces (PRA)

? PBXs and PCM channel bank

? T3 channelized access concentrators and M13 MUX

? Wireless base stations

? ATM equipment with integrated DS1 interfaces

? Multichannel DS1 Test Equipment

? T1/E1/J1 Performance Monitoring

? Voice over packet gateways

? Routers