ZL30251LDG1集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

Features

? 4 Input Clocks

? One crystal/CMOS input

? Two differential/CMOS inputs

? One single-ended/CMOS input

? Any input frequency from 9.72MHz to 1250MHz

(9.72MHz to 300MHz for CMOS)

? Clock selection by pin or register control

? Low-jitter Fractional-N APLL and 3 Outputs

? Any output frequency from <1Hz to 1035MHz

? High-resolution fractional frequency conversion

with 0ppm error

? Easy-to-configure, encapsulated design

requires no external VCXO or loop filter

components

? Each output has independent dividers

? Output jitter is typically 0.16 to 0.28ps RMS

(12kHz-20MHz integration band)

? Outputs are CML or 2xCMOS, can interface to

LVDS, LVPECL, HSTL, SSTL and HCSL

? In 2xCMOS mode, the P and N pins can be

different frequencies (e.g. 125MHz and 25MHz)

? Per-output supply pin with CMOS output

voltages from 1.5V to 3.3V

? Precise output alignment circuitry and peroutput

phase adjustment

? Per-output enable/disable and glitchless

start/stop (stop high or low)

General Features

? Automatic self-configuration at power-up from

external (ZL30250) or internal (ZL30251)

EEPROM; up to four configs, pin-selectable

? Numerically controlled oscillator mode

? Spread-spectrum modulation mode

? SPI or I2C processor Interface

? Tiny 5x5mm QFN package

? Easy-to-use evaluation software

Applications

Frequency conversion and frequency synthesis in

a wide variety of equipment types