5T9304I中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

General Description

The 5T9304I differential clock buffer is a user-selectable differential

input to four LVDS outputs. The fanout from a differential input to four

LVDS outputs reduces loading on the preceding driver and provides

an efficient clock distribution network. The 5T9304I can act as a

translator from a differential HSTL, eHSTL, LVEPECL (2.5V),

LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A

single-ended 3.3V / 2.5V LVTTL input can also be used to translate

to LVDS outputs. The redundant input capability allows for an

asynchronous change-over from a primary clock source to a

secondary clock source. Selectable reference inputs are controlled

by SEL.

The 5T9304I outputs can be asynchronously enabled/disabled.

When disabled, the outputs will drive to the value selected by the GL

pin. Multiple power and grounds reduce noise.

Features

? Guaranteed low skew: 50ps (maximum)

? Very low duty cycle distortion: 125ps (maximum)

? Propagation delay: 1.9ns (maximum)

? Up to 450MHz operation

? Selectable inputs

? Hot insertable and over-voltage tolerant inputs

? 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V),

LVPECL (3.3V), CML or LVDS input interface

? Selectable differential inputs to four LVDS outputs

? 2.5V VDD

? -40°C to 85°C ambient operating temperature

? Available in lead-free (RoHS 6) package