General description

The 74ABT652A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT652A transceiver/register consists of bus transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin (CPAB or CPBA) goes HIGH. Output Enable (OEAB, OEBA) and Select (SAB, SBA) pins are provided for bus management.

Features and benefits

■ Independent registers for A and B buses

■ Multiplexed real-time and stored data

■ 3-state outputs

■ Live insertion/extraction permitted

■ Power-up 3-state

■ Power-up reset

■ Output capability: +64 mA to ?32 mA

■ Latch-up protection exceeds 500 mA per JESD78B class II level A

■ ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

74ABT652APW屬于集成電路（IC） > 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器。恩智浦半導(dǎo)體公司制造生產(chǎn)的74ABT652APW緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動(dòng)器、接收器和收發(fā)器允許隔離對(duì)某個(gè)電路的邏輯信號(hào)的訪問，以用于另一電路。緩沖器將其輸入信號(hào)（不變或反相）傳遞到其輸出，并可能用于清除弱信號(hào)或驅(qū)動(dòng)負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進(jìn)行隔離通信。