74AC163集成電路（IC）的鎖存器規(guī)格書PDF中文資料

74AC163屬于集成電路（IC）的鎖存器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的74AC163鎖存器鎖存器是類似于觸發(fā)器的基本數(shù)字存儲(chǔ)設(shè)備，但是不同之處在于，在鎖存使能（或類似命名）信號(hào)處于有效邏輯狀態(tài)的任何時(shí)間，保持的邏輯狀態(tài)都可以改變?！巴该鳌辨i存器還允許設(shè)備輸出在鎖存使能信號(hào)有效時(shí)反映輸入的當(dāng)前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時(shí)改變。

DESCRIPTION

The 74AC163 is an advanced high-speed CMOS SYNCRONOUS PRESETTABLE COUNTER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. It is a 4 bit binary counter with Synchronous Clear.

The circuit have four fundamental modes of operation, in order of preference: synchronous reset, parallel load, count-up and hold. Four control inputs, Master Reset (CLEAR), Parallel Enable Input (LOAD), Count Enable Input (PE) and Count Enable Carry Input (TE), determine the mode of operation as shown in the Truth Table. A LOW signal on CLEAR overrides counting and parallel loading and sets all outputs on LOW state on the next rising edge of CLOCK. A LOW signal on LOAD overrides counting and allows information on Parallel Data inputs to be loaded into the flip-flop on the next rising edge of CLOCK.

With LOAD and CLEAR HIGH, PE and TE permit counting when both are HIGH. Conversely, a LOW signal on either PE and TE inhibits counting. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:

fMAX = 200MHz (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION:

ICC = 8μA(MAX.) at TA=25°C

■ HIGH NOISE IMMUNITY:

VNIH = VNIL = 28 VCC (MIN.)

■ 50? TRANSMISSION LINE DRIVING CAPABILITY

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 24mA (MIN)

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE:

VCC (OPR) = 2V to 6V

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 163

■ IMPROVED LATCH-UP IMMUNITY