74ALVCH16240DTR集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器規(guī)格書PDF中文資料

74ALVCH16240DTR屬于集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器。由安森美半導(dǎo)體公司制造生產(chǎn)的74ALVCH16240DTR緩沖器，驅(qū)動器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動器、接收器和收發(fā)器允許隔離對某個電路的邏輯信號的訪問，以用于另一電路。緩沖器將其輸入信號（不變或反相）傳遞到其輸出，并可能用于清除弱信號或驅(qū)動負載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進行隔離通信。

Low?Voltage 16?Bit Buffer with Bus Hold 1.8/2.5/3.3 V

(3?State, Inverting)

The 74ALVCH16240 is an advanced performance, inverting 16?bit buffer. It is designed for very high?speed, very low?power operation in 1.8 V, 2.5 V or 3.3 V systems.

The 74ALVCH16240 is nibble controlled with each nibble functioning identically, but independently. The control pins may be tied together to obtain full 16?bit operation. The 3?state outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are in the high impedance state. The data inputs include active bus?hold circuitry, eliminating the need for external pull?up resistors to hold unused or floating inputs at a valid logic state.

? Designed for Low Voltage Operation: VCC = 1.65 to 3.6 V

? 3.6 V Tolerant Inputs and Outputs

? High?Speed Operation:

3.0 ns Max for 3.0 to 3.6 V

3.7 ns Max for 2.3 to 2.7 V

6.0 ns Max for 1.65 to 1.95 V

? Static Drive:

±24 mA Drive at 3.0 V

±12 mA Drive at 2.3 V

±4 mA Drive at 1.65 V

? Supports Live Insertion and Withdrawal

? Includes Active Bus?Hold to Hold Unused or Floating Inputs at a

Valid Logic State

? IOFF Specification Guarantees High Impedance When VCC = 0 V?

? Near Zero Static Supply Current in All Three Logic States (40 A)

Substantially Reduces System Power Requirements

? Latchup Performance Exceeds ±250 mA @ 125°C

? ESD Performance: Human Body Model >2000V; Machine Model >200V

? Second Source to Industry Standard 74ALVCH16240