74ALVCH16244TTR集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器規(guī)格書(shū)PDF中文資料

74ALVCH16244TTR屬于集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的74ALVCH16244TTR緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動(dòng)器、接收器和收發(fā)器允許隔離對(duì)某個(gè)電路的邏輯信號(hào)的訪問(wèn)，以用于另一電路。緩沖器將其輸入信號(hào)（不變或反相）傳遞到其輸出，并可能用于清除弱信號(hào)或驅(qū)動(dòng)負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進(jìn)行隔離通信。

DESCRIPTION

The 74ALVCH16244 is a low voltage CMOS 16 BIT BUS BUFFER (NON INVERTED) fabricated with sub-micron silicon gate and five-layer metal wiring C2MOS technology. It is ideal for low power and very high speed 1.65 to 3.6V applications; it can be interfaced to 3.6V signal environment for both inputs and outputs.

Any nG output control governs four BUS BUFFERS. Output Enable input (nG) tied together gives full 16-bit operation.

When nG is LOW, the outputs are enabled. When nG is HIGH, the output are in high impedance state.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. This device is designed to be used with 3 state memory address drivers, etc.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ 3.6V TOLERANT INPUTS AND OUTPUTS

■ HIGH SPEED :

tPD = 3.0 ns (MAX.) at VCC = 3.0 to 3.6V

tPD = 3.7 ns (MAX.) at VCC = 2.3 to 2.7V

tPD = 5.1 ns (MAX.) at VCC = 1.65V

■ POWER DOWN PROTECTION ON INPUTS AND OUTPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 24mA (MIN) at VCC = 3.0V

|IOH| = IOL = 12mA (MIN) at VCC = 2.3V

|IOH| = IOL = 4mA (MIN) at VCC = 1.65V

■ OPERATING VOLTAGE RANGE:

VCC(OPR) = 1.65V to 3.6V

■ BUS HOLD PROVIDED ON DATA INPUTS

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16244

■ LATCH-UP PERFORMANCE EXCEEDS 300mA (JESD 17)

■ ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);

MM > 200V