74ALVCH16244DGG集成電路（IC）的緩沖器驅動器接收器收發(fā)器規(guī)格書PDF中文資料

1. General description

The 74ALVC16244; 74ALVCH16244 is a 16-bit buffer/line driver with 3-state outputs. The device

can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four

output enables (1OE, 2OE, 3OE and 4OE), each controlling four of the 3-state outputs. A HIGH on

nOE causes the outputs to assume a high-impedance OFF-state. This device is fully specified for

partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the

potentially damaging backflow current through the device when it is powered down.

The 74ALVCH16244 has active bus hold circuitry which is provided to hold unused or floating

data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down

resistors.

2. Features and benefits

? Wide supply voltage range from 1.2 V to 3.6 V

? CMOS low power consumption

? MultiByte flow-through standard pin-out architecture

? Low inductance multiple VCC and GND pins for minimum noise and ground bounce

? Overvoltage tolerant inputs to 5.5 V

? Direct interface with TTL levels

? IOFF circuitry provides partial Power-down mode operation

? All data inputs have bushold (74ALVCH16244 only)

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Complies with JEDEC standards:

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8C (2.7 V to 3.6 V)

? Output drive capability 50 Ω transmission lines at 85 °C

? Current drive ±24 mA at 3.0 V

? ESD protection:

? HBM JESD22-A114-A exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V