1. General description

The 74ALVCH16841 has two 10-bit D-type latch featuring separate D-type inputs for each latch

and 3-state outputs for bus oriented applications. The two sections of each register are controlled

independently by the latch enable (nLE) and output enable (nOE) control gates.

When nOE is LOW, the data in the registers appears at the outputs. When nOE is HIGH the

outputs are in High-impedance OFF state. Operation of the nOE input does not affect the state of

the flip-flops.

The 74ALVCH16841 has active bus hold circuitry which is provided to hold unused or floating

data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down

resistors.

2. Features and benefits

? Wide supply voltage range of 1.2 V to 3.6 V

? CMOS low power consumption

? Direct interface with TTL levels

? Current drive ±24 mA at VCC = 3.0 V

? MULTIBYTE flow-through standard pin-out architecture

? Low inductance multiple VCC and GND pins for minimize noise and ground bounce

? All data inputs have bushold

? Output drive capability 50 Ω transmission lines at 85 °C

? 3-state non-inverting outputs for bus oriented applications

? Complies with JEDEC standards:

? JESD8-5 (2.3 V to 2.7 V)

? JESD8B/JESD36 (2.7 V to 3.6 V)

? ESD protection:

? HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

? CDM JESD22-C101E exceeds 1000 V

74ALVCH16841DGG屬于集成電路（IC） > 鎖存器。安世半導(dǎo)體(中國(guó))有限公司制造生產(chǎn)的74ALVCH16841DGG鎖存器鎖存器是類似于觸發(fā)器的基本數(shù)字存儲(chǔ)設(shè)備，但是不同之處在于，在鎖存使能（或類似命名）信號(hào)處于有效邏輯狀態(tài)的任何時(shí)間，保持的邏輯狀態(tài)都可以改變?！巴该鳌辨i存器還允許設(shè)備輸出在鎖存使能信號(hào)有效時(shí)反映輸入的當(dāng)前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時(shí)改變。