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74LS75中文資料仙童半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書

74LS75
廠商型號(hào)

74LS75

功能描述

Quad Latch

文件大小

49.8 Kbytes

頁面數(shù)量

5

生產(chǎn)廠商 Fairchild Semiconductor
企業(yè)簡(jiǎn)稱

Fairchild仙童半導(dǎo)體

中文名稱

飛兆/仙童半導(dǎo)體公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-9 19:41:00

74LS75規(guī)格書詳情

General Description

These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable is HIGH, and the Q output will follow the data input as long as the enable remains HIGH. When the enable goes LOW, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable is permitted to go HIGH.

These latches feature complementary Q and Q outputs from a 4-bit latch, and are available in 16-pin packages.

產(chǎn)品屬性

  • 型號(hào):

    74LS75

  • 功能描述:

    INTEGRATED CIRCUIT PINOUTS

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