74LV107PWDH中文資料飛利浦數據手冊PDF規(guī)格書

DESCRIPTION

The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107.

The 74LV107 is a dual negative-edge triggered JK-type flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.

The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.

The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

FEATURES

? Wide operating: 1.0 to 5.5 V

? Optimized for low voltage applications: 1.0 to 3.6 V

? Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

? Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C

? Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C

? Output capability: standard

? ICC category: flip-flops