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74LV7032APW-Q100中文資料安世數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

74LV7032APW-Q100
廠商型號(hào)

74LV7032APW-Q100

功能描述

Quad 2-input OR gate with Schmitt trigger inputs

文件大小

203.95 Kbytes

頁(yè)面數(shù)量

10 頁(yè)

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中文名稱

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更新時(shí)間

2025-1-18 10:02:00

74LV7032APW-Q100規(guī)格書(shū)詳情

1. General description

The 74LV7032A-Q100 is a quad 2-input OR function with Schmitt-trigger inputs, capable of

transforming slowly changing input signals into sharply defined, jitter-free output signals.

Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed

voltage environments.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

? Automotive product qualification in accordance with AEC-Q100 (Grade 1)

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C

? Wide supply voltage range from 2.0 V to 5.5 V

? Maximum tpd of 9.5 ns at 5 V

? Typical VOL(p) < 0.8 V at VCC = 3.3 V, Tamb = 25 °C

? Typical VOH(v) > 2.3 V at VCC = 3.3 V, Tamb = 25 °C

? Supports mixed-mode voltage operation on all ports

? IOFF circuitry provides partial Power-down mode operation

? Latch-up performance exceeds 250 mA per JESD 78 Class II

? ESD protection:

? MM: MM JESD22-A115-B exceeds 200 V

? HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4 kV

? CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 2 kV

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TI
05+
SSOP-14
77
詢價(jià)
原裝
1922+
SOP145.2
12600
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TI/德州儀器
23+
SOP14-5.2
50000
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PHI
1844+
SSOP-14
9852
只做原裝正品假一賠十為客戶做到零風(fēng)險(xiǎn)!!
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HIT
24+
SOP5.2
35200
一級(jí)代理/放心采購(gòu)
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TI/德州儀器
22+
TSSOP14
25000
只做原裝,原裝,假一罰十
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PHILIPS/飛利浦
23+
SSOP-14
18702
原廠授權(quán)代理,海外優(yōu)勢(shì)訂貨渠道??商峁┐罅繋?kù)存,詳
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PHIL
NA
8560
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FSC
2020+
SSOP14
80000
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PHI
22+
SSOP-14
5000
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